1) Field of Invention
The invention relates to stitching (strapping) methods of forming high-density Metal/polysilicon Oxide Nitride Oxide Silicon (MONOS) memory arrays with reduced bit line resistance, reduced control gate resistance and reduced word gate resistance using three-level metal lines, resulting in high density MONOS memory arrays with high performance
2) Description of Prior Art and Background
Twin MONOS structures were introduced in the U.S. Pat. No. 6,255,166, and U.S. patent applications Ser. No. 09/861,489 and 09/595,059 by Seiki Ogura et al. and also various array fabrication methods of the twin MONOS memory array were introduced in U.S. Pat. Nos. 6,177,318 and 6,248,633 B1 and U.S. patent application Ser. No. 09/994,084 filed on Nov. 21, 2001.
The twin ballistic MONOS memory cell, illustrated in FIG. 1A, may be arranged into a bit diffusion array as follows: each memory cell contains two nitride regions 031 which comprise storage elements for one word gate 040, and half a source diffusion and half a bit diffusion (003). The diffusion junctions are shared by two adjacent storage elements. Control gates can be defined separately (042) or shared together (043) over the same diffusion (003). The control gate is electrically isolated from the underlying diffusion junctions. Diffusions are shared between cells and run in parallel to the sidewall control gates (042), and perpendicular to the word line (041). The diffusion lines become bit lines.
In a conventional MOSFET memory, a transistor structure consisting of one polysilicon gate between source and drain diffusions is used and word gate polysilicon line and diffusion bit lines are orthogonally placed. When the memory array gets large, the bit line (BL) and word gate line (WG) become long. The word line resistance due to the series of word gates is high in large memory devices. In order to reduce word line resistance, it is necessary to connect the word line periodically to a metal line that runs in parallel to the poly word lines. This is referred to as a xe2x80x9cstitchedxe2x80x9d or xe2x80x9cstrappedxe2x80x9d word line. Also the bit diffusion line can be sub-arrayed and the bit line can be xe2x80x9cstitchedxe2x80x9d by a conductive metal line. In a typical memory, each polysilicon word line is stitched to a metal word line which runs on top of each poly word line, and each diffusion line, which runs orthogonally to the word lines is stitched by another layer of metal line.
However, in the high-density twin MONOS cell shown in FIG. 1A, the transistor consists of three gates between source and drain diffusions. Three resistive layers of control gate and word gate and bit diffusion may need to be stitched to reduce resistance and to achieve the target performance. For higher density, the polysilicon control gate lines and diffusion bit lines may run in parallel to and on top of each other. If the cell is metal-pitch limited and requires stitching, that means that two additional layers of metal lines have to run on top of and contact to the two resistive layers. This is a layout and process challenge, as it is not possible to stitch two resistive layers to two respective metal layers when the set of the composite four lines are running on top of each other within the minimum metal pitch.
In the memory cell described hereinabove, however, another third resistive layer is added and stitched by the third level metal. Then a clever three-dimensional solution makes it possible to stitch three resistive layers by three metal lines.
An objective of the present invention is to provide a new method of stitching between high resistance lines and low resistance metal lines in a memory cell having three types of high resistance lines.
Another objective of the present invention is to provide a new method of stitching such that the three high resistance lines can be stitched by three low resistance metal lines within a cell size that is limited by the minimum metal pitch.
Yet another objective of the present invention is to provide a method of forming the stitch contact areas for the high resistance line.
A further objective of the present invention is to provide a method of stitching three high resistance lines to low resistance metal lines while providing bit line select transistors.
A still further objective of the present invention is to provide a method of stitching three high resistance lines to low resistance metal lines while providing bit line and control gate select transistors.
In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches.
When the memory becomes too large, the total capacitance of the bit line also becomes too large and the RC time constraint becomes too large for a specific application speed. Therefore, the bit line needs to be subdivided into several sections. Each section is selected by placing a select transistor at each end of the subdivided section. Thus, the total bit line capacitance is reduced to the sum of the global metal line capacitance and the selected section of devices. Also the above stitching invention is extended to the case of placing select transistors on the bit line. Also another stitching method for the deviated array structure provided in U.S. patent application Ser. No. 09/994,084 is also presented using a similar method. FIG. 2 provides a conceptual illustration of a memory cell array having control gate lines 142 and bit lines 103 running in parallel to each other, and the word gate line 140 perpendicular to both the control gate and bit lines. Word gate polysilicon lines are stitched to metal. The diffusion bit line is further divided into a sub-array by a bit line select transistor 196, which connects to a main bit line. The control gate polysilicon line is also divided into a sub-array by a control gate line select transistor 195, which connects to a main control gate.
The first embodiment of the invention provides a stitching method of three resistive layers to three conductive layers where two resistive layers (003,042) run on top of, and in parallel to each other, and the third resistive layer (040) runs orthogonally to the first two resistive layers (FIG. 3). The cell width and height allows for one conductive metal in both the vertical and horizontal directions. Each resistive layer is periodically contacted (stitched) by a respective upper conductive layer to reduce the total resistive layer resistance. In order to reduce resistance, the middle resistive layer 2 (042) is periodically connected to the conductive layer 061 (M1), which is above it. In order to make a connection between the bottom resistive layer 1 (003) and the uppermost conductive layer M3 (081), the second resistive layer 2 (042) is cut and separated in order to expose the bottom resistive layer 1 (003). Then a contact/via stack is built up from the bottom resistive layer 1 (003) to the top conductive layer 3 (M3) 081. The two ends of the second resistive layer 2 (042) are connected together by contacting to the second conductive layer M2 (071). This second conductive layer M2 (071) wire bypasses the contact/via stack by using the open space of the adjacent cell. This bypass path will hereafter be referred to as a xe2x80x9cloopxe2x80x9d. Since this bypass loop of second conductive layer M2 (071) blocks contact to the bottom resistive layer 1 (061), the stitch is placed on every other set of composite lines. The unstitched lines may be stitched at another location, a short or far distance away. Thus by utilizing one extra conductive metal layer, two resistive layers can be stitched to two conductive layers, when all four layers run in parallel to and on top of one another. The extra second conductive layer M2 (071) is used only in the stitch area, and may otherwise be used in the other areas to stitch between the third resistive layer 3 (040), which runs orthogonally to the first and second resistive layers 1 (003) and 2 (042). For this explanation, in order to reduce the resistance of the resistive layers, conductive layer 1 (061) stitches to resistive layer 2 (042); conductive layer 2 (071) stitches to resistive layer 3 (040) and conductive layer 3 (081) stitches to resistive layer 1 (003). In the loop, conductive layer 2 (071) is used to bypass the contact stack and connects the cut edges of resistive layer 2 (042) together. However, it is also possible to exchange the function of conductive layer 1 (061) and conductive layer 2 (071), and stitch them to resistive layer 3 (040) and resistive layer 2 (042), respectively. Thus three resistive layers may be stitched by three conductive metal layers within minimum cell/metal pitch.
In the second embodiment, in a diffusion bit array of the twin MONOS memory where the memory device structure is fabricated as described in U.S. Pat. No. 6,248,633 B1, the bit diffusion contact for stitch 151 is formed. Then by utilizing the resistive to conductive layer stitching method which was described in the first embodiment scheme, the control gate polysilicon 143 is stitched with Metal 1 (161) and at the line edge, as shown in FIG. 5B. In the array, metal 2 (M2) 171 is used to lower the resistance of the polysilicon word gate line. However, in the stitch area, as demonstrated in FIG. 5C, M2172 is also used to connect the edges of the severed CG lines that are contacted to Metal 1 (M1) 161. The M2 line loops around the contact/via stack 151, which connects the diffusion bit line 103 to the parallel running Metal 3181 in FIG. 5D. Since the loop of M2171 blocks the bit line contact in the adjacent cell, the stitch region contacts alternate bit lines and alternate CG lines. The uncontacted set of lines may be stitched immediately below in a separate stitch area or at the other end of the sub array. It is also possible to interchange the functions of metal 1 and metal 2 for this array, such that metal 1 is used to contact to the word line and for the stitch loop, and metal 2 is used to stitch to and reduce the resistance of the control gate line.
In the third embodiment of this invention, the stitching method also incorporates a bit diffusion select transistor and/or a control gate line select transistor. The purpose of the select transistors may be to reduce the overall capacitance of the bit line or control gate line, or to limit the disturb conditions that a grouped sub-array of cells may be subjected to during program and/or erase. These select transistors are added into the stitch areas between memory cell sub-arrays. FIG. 8A and FIG. 9C show an implementation example of a bit line select gate 211 and control gate select gate 212 in the stitch area. Referring to FIGS. 7A-E and 8A, the stitch areas on both sides of a sub-array are shown. Bit line select gates 211 are placed closest to the array and the control gate select gates 212 are placed outside of the bit line select gates from the array. At the end of the sub-array, the bit diffusion is extended past the edge of the control gate by implanting N+ species such as As prior to formation of control gate sidewalls (FIG. 9A). The bit diffusion extension 204 and bit select transistors 211 are provided alternatively on both sides of the sub-array. Select transistors are isolated from each other by shallow trench isolation. (FIG. 7E and FIG. 8A) The bit select gate 211 is placed horizontally across the extended bit diffusion and the horizontal gate becomes the bit select gate. The diffusion on the other side of the bit select transistor gate is connected to the main bit line by a contact stack 251 between the diffusion to second level metal 2 (271) as shown in FIG. 9A. When control gate select transistors 212 are also needed, a pair of control gate select transistors 212 are placed out of phase, and between the two bit line select transistors 211 inside the two edges of two sub-arrays. The pair of control gate select lines run parallel to the word gate and perpendicular to the bit line and control gate lines (FIG. 8A). The center contact 254 between two control gates 212 becomes the control gate connection point to the main control gate line which runs vertically in metal M3 (281), as illustrated in FIGS. 8A and 8D. The other diffusion region of the control gate select transistor is locally connected by metal M1 (261) to the other end of the polysilicon control gate stitch 252. (FIG. 8B) Main bit lines run in metal 2 (271), but near the main CG contact, they are cut and connected down to metal 1 (261), in order to loop around the main control gate contact 254 to complete the bit stitch (FIG. 8C). Thus at the one edge of sub-array space, alternative bit select gate/stitch via M2 line and control gate select/stitch via M3 may be completed using a M1-local connection and loop. Metal 1 may also be used in the array region to stitch the word gate lines at intervals to reduce the polysilicon word gate resistance. This example shows a bit select transistor and control gate select transistor. Using the same contact and metal wiring approach, it is also possible to implement the stitch and select area with transistors for only bit line selection or with transistors for only control gate line selection.
The fourth embodiment shows a stitching method in another type of array arrangement called xe2x80x9cmetal bitxe2x80x9d where the diffusion of each cell is connected to first level metal (M1) 361 by a contact 351 (see FIG. 10C, FIG. 11B, and FIG. 12B). The polysilicon control gate lines 342 and the polysilicon word gate lines 340 run parallel to each other and orthogonally to the bit metal line 361FIG. 12. A polysilicon pad is prepared in order to contact between the control gate polysilicon and metal (FIGS. 10A-C). This polysilicon pad 343 is formed by using the self-aligned methods described in the previous embodiment. Metal M2371 is used to stitch control gate 342 (FIG. 11C) and the metal M3381 is used to stitch the word gate 340 (FIG. 11D). The word gate contact 355 is placed in the open space which is created by cutting the control gate M2 line and looping around in metal 1 in order to avoid the word gate contact area (FIG. 11C). By shifting the metal 2 and metal 3 lines half a metal pitch and looping with M2 as well as M1, every control gate line 342 and every other word gate line 340 can be contacted within the same region (FIG. 12A). Since the control gate line is a narrow sidewall polysilicon with higher resistance than the word gate line, the ability to stitch to every CG line on both ends of the sub-array is beneficial for high performance applications.